How to use HPS internal clock in Agilex 7 SOC

Hi Veerappan,

Sorry for the hold up, I've checked with our embedded team and also factory guy on this regarding the documentation mentioning about internal OSC usage and also testing out the Quartus

Internal OSC is not available as source for both main and peripheral PLL.

The confusion is actually because of the documentation statement that mentioned about the inputs to PLL but on the note below, it does mentioned that Internal OSC cannot be used under normal circumstances. Internal OSC is meant for bring up HPS, after bring up HPS will switch to HPS_OSC_CLK

even though you configured at Device and pin options to use internal OSC

but in HPS QSYS, main PLL and peripheral PLL input clocks (under internal clocks and output clocks tab) are limited to external OSC or FPGA to HPS free clock(if enabled) only

enable FPGA-to-HPS free clock (input clocks tab)

Hope that clears up the OSC issue not locking and still remaining default to External OSC when reading the register back.

Thanks and sorry for the delay in getting back on this.

Regards

Kian