Forum Discussion

matif's avatar
matif
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to use FPGA side SDRAM on Cyclone V SoC

​Hi, There are two SDRAM (each of 1GB) on cyclone V SoC (Arrow Sockit Board (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816)) (5CSXFC6D6F31C8ES), one for HP...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi matif,

To perform memory simulation, you can refer to Chapter 8. Simulating Memory IP on page 468 of this handbook which have all the step by step instruction in order to run calibration. --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf

The following table lists signals produced by the calibration process to show on the calibration pass/fail result.

Here is some additional info that I think is useful which to share with you. 😊 If you're interested to know more details on the UniPHY IP calibration stages, you may refer to Chapter 1.17. UniPHY Calibration Stages (page 55) of this handbook --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf

Thanks

Regards,

NAli1

matif's avatar
matif
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

​Hi,

thank you for the support. I did the calibration checks on my board and calibration tests are all fine. Now I wana do simualtion but simulation is not fine. I followed the steps in the documents as you provided. Here is a screen shot. Any ideas on what I can do.