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matif's avatar
matif
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to use FPGA side SDRAM on Cyclone V SoC

​Hi, There are two SDRAM (each of 1GB) on cyclone V SoC (Arrow Sockit Board (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816)) (5CSXFC6D6F31C8ES), one for HP...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello matif,

Also, here is some additional debug suggestion from me 😊

As I can see that everything looks perfect in your qsys connection attached. So, perhaps you can try to run the calibration and see if it pass/fail.

Next, I will suggest you signaltap (stp) the avalon-MM interface and check which signal is not behave unexpected causing the code to stuck.

Thanks

Regards,

NAli1

matif's avatar
matif
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi,

thank you so much for your reply. Can you give me some example link on how to do calibration for pass/fail?

And all the GSRD or GHRD designs I have seen so far just implement design of either SRAM or SDRAM on HPS but what I need is an example that show me how to use SDRAM particularly only on FPGA side.