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Honored ContributorHow to set up a transceiver in Arria V GX development kit?
Hello,
I have the Arria V GX 5AGXFB3H4F40C5. I program it with Quartus II 13.1 in windows 8.1 the questions are at the end of this message. I'm trying to set up one transceiver as transmitter TX with only one channel which works at 1GHz or 800Mhz, frecuency must be selected by the user pressing the push buttons. That's why I add one Reconfiguration Controller in the block design file for the Native PHY Transceiver IP Core, also I add the Reset Controller too. So I have got 4 blocks in the desing file: The Reconfiguration Controller, the Reset Controller, the Tranceiver IP Core and my own logic block (written by me in VHDL) My logic block receives the pressed signal from the push button and then sends the needed data to the reconfiguration controller for switching the frecuency of the Transceiver. i have read the transceiver's section in the manual, so i think i know how to use the avalon memmory mapped system for reconfiguring the pll reconfiguration registers.
I have used the Derive PLL clocks function and the Derive Clock Uncertaintly. I have saved it in de sdc file, I have added the sdc file to the project and recompiled it again. the questions are:
Which is the pin number I must assign to my signal tx_serial_data in the assignment editor? I searched it in the manual and I didn't find it. SMAs ports don't send any signal. Now I have assigned the PIN_J3 but It's not working. Why do I have this warnings? Specialy the last one Warning (332043): Overwriting existing clock: alt_cal_av_edge_detect_clk Warning (332174): Ignored filter at Trans5.out.sdc(94): sv_reconfig_pma_testbus_clk_0 could not be matched with a clock Warning (332035): No clocks found on or feeding the specified source node: inst1|controlador_inst|basic|a5|reg_init[0]|clk Warning (332060): Node: transmisor:inst|altera_xcvr_native_av:transmisor_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT was determined to be a clock but was found without an associated clock assignment. Can anyone give me a link to a tutorial for setting up this trasnceiver in this FPGA? Can I send signals at less frecuency than 800mhz with the Native Transceiver PHY IP Core?
