Contributor
Super ContributorHPS peripherals are accessed by FPGA logic through the F2H bridge, which it looks like you've enabled but not connected to anything (f2h_axi_slave). An address map is set up so the FPGA logic can access the HPS peripherals through normal memory-mapped addressing.
ContributorHow can I do that? Can you help?
Super ContributorYou make connections in Platform Designer to IP you add to the system there or export the interface and connect to HDL code you write through port mapping. You should learn more about how to use Platform Designer to help understand what you need to do. You can start here:
