How to recompile verilog code with slight change in reg value using previous fitter(Place & route)

I try your suggestion to logic lock and design partition on the intended module/instance of the verilog code on the working compilation. Once i box them, i recompile with a purpose to export out the qxp file. But i notice once i box it and recompile, the cells of the module in the floor plan is no longer matching the initial place and route. Seem that by boxing the intended module without changing the verilog code will cause the fitter to place and route differently in the floor plan.

Is this a normal behaviour of the fitter that logic lock and creating the design partition will cause the place and route to change?