Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThose messages just mean that you either have an overlap in addresses or the base address isn't aligned to the correct boundary. So if you had a slave port that takes up 16 bytes of address span the only places it can be places in the address space are 0, 16, 32, 48, 64, etc....
If the signals you have added to the signal tap trace show up in red after you compile the design that means they have been optimized away (and so they won't toggle when you sample them). There are different ways to prevent this but what I typically do is just make a copy of my work and for the nets that I care about I just add the (* keep *) attribute to the net deceleration like these: (* keep *) wire <net_name>; (* keep *) reg <variable_name>;