How to make RSFEC IP work in Stratix10 device?

HI,

1. May I know which Quartus version that you are using ?
2. Stratix 10 FPGA contains few Ethernet IP. Are you referring to "low latency 100G Ethernet Intel FPGA IP" or some other Ethernet IP ?
3. Do you encounter the issue in simulation or actual hardware testing ?
4. Can you elaborate further on your loopback testing ?

• Where do you enable the loopback path ?
  • Do you observe data transfer on Tx path as you claim there is no data return on Rx path ?

1. Have you tried debug using Ethernet example design that you can generate from Ethernet IP to see whether issue still persist ?
2. I found some known issues with the RS-FEC feature but not sure related to your issue or not

• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-the-low-latency-100g-ethernet-intel--stratix--10-fpga-i.html
  • https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/why-does-the-generated-example-design-of-100g-ethernet-soft-ip-w.html

Thanks.

Regards,

dlim