How to infer a FIFO using registers/ALM and not block RAM ?

You can set the FIFO parameter setting use_eab to OFF. You may checkout the FIFO UG below.

https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-parameter-settings.html

You may try to set the ramstyle attribute to logic, to implement it in logic cells.

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram.htm#:~:text=A%20Verilog%20HDL%20synthesis%20attribute,to%20the%20ramstyle%20synthesis%20attribute.

Do you able to get the desired behavior?

Using the attribute still inferred memory with M20K. I alternatively instantiated a RAM (from intel IP) and then used the instantiation as memory to build my FIFO. I am able to generate a ALM based memory in this case.

That works as well. I trust that you will proceed with the alternate solution that you have found.

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos and select the best solution.