rgodwNew Contributor6 years agohow to increase the data width of an input i have to complete a signed n-bit adder. the inputs are STD_LOGIC_VECTOR((DATA_WIDTH-1)downto 0) and output is STD_LOGIC_VECTOR((DATA_WIDTH)downto 0) i was told to do it as by increasing the datawidt...Show More
Vicky1Regular Contributor6 years agoHi,May I know any update or should I consider that case to be closed?Regards,Vicky
Recent DiscussionsStratix 10 GX SI Board - issue with the Board Test System (BTS)About PCIe Daughter Cards for Agilex™ 3 FPGA and SoC C‑Series Development KitDE10-Lite unable to flash?Available replacement for the discontinued P/N: MK-A5E065BB32AES1 ?Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit