Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- problem is that the Verilog Function uses the SRAM to Store Data and change Data and use the Data to do more other things --- Quote End --- I don't see what the problem is. If the SRAM is an Avalon slave and your custom verilog and NIOS CPU are both masters, both your custom verilog and NIOS CPU can access the SRAM. SOPC builder will automatically provide arbitration logic.