New ContributorHow to get a 644 MHz clock on the Arria 10 SoC Dev Kit?
Hello,
I’m trying to get the Ethernet 1G/10G MAC example design to run on the Arria 10 SoC dev kit. The document here (https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-20016.pdf, page 33, Figure 20) indicates that an external clock of 644.53125 MHz for “pll_ref_clk_10g” is among the required clocks. However, I’ve had trouble finding a suitable clock.
First of all, I can only connect the “pll_ref_clk_10g” signal to one of the clock pins in the columns 28/29 (as shown in Quartus’s Pin Planner) that are labeled as “dedicated transceiver”. Among them, I found only 2 pairs of LVDS clock pins that are configurable with the ClockController.exe tool (that comes with the Arria 10 SX SoC Package Installer):
• PIN_AG29/28
• PIN_G29/28
These pins come from U50, which in the schematic is shown to be Si5338B-CUSTOM. Unfortunately, according to the datasheet of the Si5338 device (https://www.silabs.com/documents/public/data-sheets/Si5338.pdf, page 37), an Si5338B can output only a maximum frequency of 350 MHz. I also wrote some test code that uses the clocks to blink an LED. Whenever I used ClockController.exe to set the frequency higher than 350 MHz, the LED would stop blinking.
Then I looked at the clocks from U26, as shown in the Figure 5-3 of the Arria 10 SoC Dev Kit User Guide. I found 2 pairs of clock signals from U26 that are readily connected to the FPGA: PIN_L29/28 and PIN_AR29/28. However, one pair seems to have a frequency of ~400 MHz and the other one seems to have a frequency that is even much lower.
Any advice?
Thanks,
Binh
