How to get a 644 MHz clock on the Arria 10 SoC Dev Kit?

Hello Anand,

Thank you for your reply.

The U42 CLK_3Ep & CLK_3En pins connect to the W5 & W6 pins of the FPGA. When I tried connecting the "ref_clk_10g" signal to the W5 & W6 pins, I got the following errors during the Planning stage of the compilation:

* Error (11192): Input port "REF_IQCLK[0]" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" cannot connect to PLD port "O[0]" of "IO_INPUT_BUFFER" for atom "ref_clk_10g~input".

* Error (11192): Input port "REF_IQCLK[0]" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" cannot connect to PLD port "O[0]" of "IO_INPUT_BUFFER" for atom "ref_clk_10g~input".

It seems that the high speed ref clock signal can connect only to pins in the columns 28/29 labeled as "dedicated transceiver" of the FPGA.

Furthermore, when I created test code that uses the U42 pins for blinking an LED, the LED would stop blinking as expected whenever I used the ClockController.exe program to increase the clock speed to over 250 MHz.

Thanks

Binh