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- AnandRaj_S_Intel
Regular Contributor
Hi,
Regarding gate count, most of the dev kit will typically be very large, hopefully much larger than our design. We can utilize a max of 60-70% FPGA resources.
Key here is memory requirement,
The Quartus tools will estimate for you how many gates your design requires.
- So we can design HDL with Nios II project for a specific FPGA device with Quartus tool and check the resource utilized.
- Also, need to check hardware interfaces required with respect HDL design & IP's.
Regards
Anand