Forum Discussion
Occasional ContributorHow to connect fpga subsystems w/o using physical fpga pins
The All Pins list at the bottom of the Pin Planner shows all the top-level I/O signals as determined by Quartus that you can connect to I/O pins, not the signals that you've assigned to physical I/O pins of the device. Again, if this is not what you expect for signals that should get connected outside the device and that most of these 117 are supposed to be internal signals, then it is probably because you have used the pin symbol in the schematic editor on all of these signals. The reddish brown pins you see in the package view (the graphical view of the chip) are the manual pin assignments that you created. You don't have to assign all the signals in the All Pins list to physical I/O pins, but again, they are showing up there because Quartus thinks they are top-level I/O that need pin location assignments.
As for the design schematic, you have to add names to the wires. Right-click a bus, go to Properties, and add the name. The end of the bus/wire will have an x on it and will connect to another bus/wire with the same name.
Super ContributorWhat you see in Pin Planner are the Fitter placements for the top-level I/O (they're green, right?). If you don't make any manual pin assignments, the Fitter selects locations for the top-level I/O because if you compile the design and then program the device, hardware pins need to be selected. Fitter pin assignments are not written to the project .qsf file unless you back annotate them.
If you don't want any connections to hardware pins (though I'm sure you will eventually; just make manual assignments in the Pin Planner), add Virtual Pin assignments in the Assignment Editor to the I/O in question.
BillM256Hi Sstrell,
As always, many thanks for your help. I’ve embedded answers to your questions in red. I think your Virtual Pins are the solution, but I’ll keep issue open a little longer in case someone can offer more.
My best,
Bill
What you see in Pin Planner are the Fitter placements for the top-level I/O (they're green, right?). As I understand, they’re a variety of colors. I’ll provide an inventory if you want. If you don't make any manual pin assignments, the Fitter selects locations for the top-level I/O because if you compile the design and then program the device, hardware pins need to be selected. Fitter pin assignments are not written to the project .qsf file unless you back annotate them.
If you don't want any connections to hardware pins (though I'm sure you will eventually; Yes! But there are way too few pins to connect all subsystems. just make manual assignments in the Pin Planner), add Virtual Pin assignments Looks like Virtual Pin assignments is what I need. I’ll research. in the Assignment Editor to the I/O in question.
