Forum Discussion

shvlad's avatar
shvlad
Icon for New Contributor rankNew Contributor
6 years ago

How to configure DSP block in "three 9x9 multipliers" mode?

Hi everyone Please help me configure DSP block in "three 9x9 multipliers" mode. I have a Cyclone V family chip, I've read this document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, Thanks for sharing the QAR. Based on my understanding, the way 1 seems to be the right way for the implementation. I am able to replicate the observation of 3 DSP blocks being used in compilation. For your information, as I added logic lock region with only 1 DSP in the chip planner, and assign your design to it, the compilation is able to fit the three 9x9 multipliers into a single DSP block. For your information, generally if there are still sufficient DSP blocks in the device, the compilation will choose to utilize more DSP blocks for better timing and performance. Fitter will only try to pack into a single DSP block when there is limited DSP resources. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
shvlad's avatar
shvlad
Icon for New Contributor rankNew Contributor
6 years ago

Your answer is totally right!

I created this code

`timescale 1ns / 1ns
 
(* multstyle = "dsp" *)
module mux_9x9
#(
	parameter L = 25
)
(
	input logic [8:0] x_0[L],	
	input logic [8:0] x_1[L],
	input logic [8:0] x_2[L],
 
	input logic [8:0] y_0[L],	
	input logic [8:0] y_1[L],
	input logic [8:0] y_2[L],
	
	output logic [17:0] p_0[L],	
	output logic [17:0] p_1[L],
	output logic [17:0] p_2[L]	
);
 
genvar i;
generate
	for( i = 0; i < L; i++ )	
		begin:MULT			
			assign {p_0[i],p_1[i],p_2[i]} = {x_0[i]*y_0[i],x_1[i]*y_1[i],x_2[i]*y_2[i]};				
		end	
endgenerate
	
endmodule

Quartus places three multi to one DSP when it doesn't have enough DSP (just change parameter "L").