Forum Discussion
Altera_Forum
Honored Contributor
16 years agoJust to clarify, there are two NiosII/CycloneIII reference designs:
Cyclone III Starter Kit (CIIISB): cycloneIII_3c25_start_niosII_standard NiosII Embedded Evaluation Kit, Cyclone III Edition (NEEK): cycloneIII_3c25_noisII_standard These two designs are quite different. The original post was about the CIIISB example, not the NEEK example (but the NEEK example runs on the CIIISB as well). The file posted by jakobjones is for the NEEK example. I tried following his instructions. I found that I had to include this line at the top of his .sdc file: create_clock -period 20.000 [get_ports {top_clkin_50}] With this small change the compilation under Quartus 9.0 went well. I saw the same behaviors that he reports, except that the only timing failures were associated with the JTAG clock.