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Occasional ContributorHow to add pull-ups on DE10-nano GPIO
I'm trying to add weak pull-ups on JP7 GPIO1 of DE10-nano board.
The board boots to Linux so as far as I understand FPGA image is loaded by Uboot from the rbf file on boot partition.
There is a Default FPGA project provided with DE10-nano, however, GPIO pins are not assigned in this project.
What am I missing here? Is this the correct project? Which settings map between Cyclone pins and GPIO accessed by HPS and how to modify them to enable weak pull-ups?
Thanks
25 Replies
SreekumarR_G_IntelFrequent Contributor
you can make sure board revision and the file meant for the board are same .
Anyhow good news is you are able to boot it ; Now try modifying the working rbf design files and see any changes in the led.
I cant say what may be issue until fully compare the hardware and the software built for it .
Thank you ,
Regards,
Sree
jackhabMy board revision is C0 and I verified the CD package I downloaded matches the HW revision.
What do you mean by " try modifying the working rbf design files"? If I try to modify Default Quartus project from the CD and create new RBF file it cannot be loaded by U-Boot.
- SreekumarR_G_Intel
Once you create the RBF , are you uboot using the hw_sw hand off file ?
Regards,
sree
- SreekumarR_G_Intel
Sorry..I was in hurry..anyway what i mean is ..once you modify Default Quartus project from the CD and create new RBF file , Did you create the new uboot.img, preloader and other files .
Thank you,
Regards,
Sree
- jackhab
I just found the correct FPGA project for DE10-nano is in https://github.com/intel/de10-nano-hardware.git
Thanks for the support, Sree.
