Occasional Contributor
Frequent ContributorHello ,
you can include in two ways ;
i) use the qsf assignment tcl script to add pull up as smillar to the FPGA.
ii) or you can use the pin planner
iii) or you can use the assignment editor
Here is the document i got through google which include picture by picture
https://sites.ualberta.ca/~delliott/ece492/appnotes/2013w/GPIO_internal_pullup_resistor/AppNote_GPIO_Internal_Pullup_Resistor.pdf
Thank you ,
Regards,
Sree
Occasional ContributorHi Sree
I found a project on DE10-nano CD (in \Demonstrations\FPGA\Default). The board User Manual refers to this project as manufacturer default.
It has all the GPIO pins and adding pull-ups is quite straight forward in Quartus.
When I compile it and convert SOF to RBF file for U-Boot to load, U-Boot fails to load device tree (I get ERROR: Did not find a cmdline Flattened Device Tree message via COM port) although the same device tree file is in the same place on SD card.
Does creating RBF for DE10-nano requires any special steps?
