How to access SRAM on CycloneIII dev kit - not via nios !

thank you for the reply.

let me rephrase the issue.

I don't want to write and read simultaneously. it's filling the memory first, and then read it.

I'm trying to use the test code:

/////////////////////////////////////////////

always @(posedge osc_clk or negedge reset_n)

if (~reset_n) begin

ram_cnt <= 0;

end

else begin

ram_cnt <= ram_cnt + 1;

end

assign ssram_adsc_n = 1'b0;

assign ssram_ce_n = 1'b0;

assign flash_ssram_a = ram_cnt[9:1];

assign ssram_bwe_n = ram_cnt[10];

assign ssram_oe_n = ~ram_cnt[10];

assign flash_ssram_d = (ssram_oe_n) ? ram_cnt[9:1] : 32'bZ;

/////////////////////////////////////////////

the code should simply fill each address with a consecutive number.

however, although the write sequence is 0,1,2,3,4,5,6,7,8,9,10,11 (inc per clk). I see that on the output the data lines show -1,-1,-1,-1,3,3,3,3,7,7,7,7,9,9,9,9,11,11,11,11 etc.

all I need is an example of code (Verilog or VHDL, not C) that will allow writing of a streaming data (60MHz, if it is relevant) into the SSRAM. and an example of how to read it in a stream after than.

thanks