How can we generate a design for FPGA2 on Stratix V Advanced Systems Development Kit without any timing violations within the DDR3 SDRAM Controller IP Component?

Hi CEnde,

Stratix V EMIF using soft memory controller and the timing is sensitive to pin location.

The dev kit is develop prior to timing model finalized. Thus, the pin location of the dev kit cannot change after timing model is finalize and we aware that timing is not fully clean with that pin location.

However, since dev kit is work in typical condition (typical voltage and temperature). Thus, it is still work reliable even timing is not clean. Therefore, it is still acceptable even timing is not clean since the design is work correctly on the board.

However, if customer develop their customer board, we advise to get a pin location that meet timing, then only tape-out their board design.

Sincerely hope this explanation is making sense to you.

Thanks