Forum Discussion
SreekumarR_G_Intel
Frequent Contributor
6 years agoHello Ross,
Thank you for questions,First I apologize for my delayed response.
i am not sure why you are looking for pull down options , Here is the cyclone V pin out guidelines link below
This is used to find the state the pin should if the pin are unused and also information about any external pull up /pull down requirement for Cyclone V.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
About the Bus hold ,
good question.
From the block diagram of the IOE reference to figure 5-10,
Assuming you have output (low impedance) of logic 1 and it set to hold the value...when you change to input buffer (i.e high impedance) i think there will be no problem to hold the logic if i understood correctly..but honestly i never tried on inout port.
Can you kindly try and let me know ?
Also let me know any if you have any other questions related to same topic ?
Thank you ,
Regards,
Sree
RLee42
Occasional Contributor
6 years agoHi Sree,
Thank you for your information.
Actually, I'm using an existing board that has a cyclone V device on it. I'd just like to have some input PINs to keep logic 1 and some others to keep logic 0 when there are no connections. I do it by program instead of hardware currently and I'd like to know if there are some other better ways to achieve this.
I also have interests on the features that I haven't used before, so I'll have a try to know about the Bus hold after this busy period and give you a feedback if I have any conclusion.
Thank you.
Best regards,
Ross