Hi .. I'm a student and I'm working on a project which involves a design that has NiOS II processor, DDRSDRAM, SSRAM, a custom Ethernet MAC and other components and I've to run an application on it.. I use NiOS II embedded Evaluation board(Cyclone III), quartus 8.1 web edition. Since I'm new to Altera, I would like to start with a simple design with an ethernet MAC , then send and recieve packets through it. I'm not strong in Ethernet concepts too. I feel that the design with TSE MAC and socket server example are too high at this level of me to understand. So can anyone send me a design which has a MAC and also tell me how to send and recieve packets over it? If possible, can you send me supporting documents for mastering the concepts of ethernet. Thanks and Regards Renu:)

This seems to be a recurring theme. People are wanting something simpler than the ethernet example that Altera is offering. I really think that the Simple Socket Server example is the quickest and easiest way for you to get ethernet running. What part of it specifically is making you hesitate? As an alternative to the TSE MAC, I would recommend using the "Avalon OpenCores MAC". http://www.alteraforum.com/forum/showthread.php?t=3665 And not just because I made the port. It's one single drop-in component vs. the 4-5 required for the TSE MAC. It's easier to use. And it should drop right in and work with the Simple Socket Server example. One thing I would like to do when I get a little time, is create a simpler more useful ethernet example design for hardware engineers. Something that would allow them to usefully interface with hardware. But until I get the time to do it, I recommend starting with the simple socket server. The other thing people are asking for is a patch to allow them to run the InterNiche stack without uC/OSII. Again, when I get the time. Jake

Hi... Where could I get the PHY address of DP83848C PHY of Nios Embeeded Eval Kit? I couldnt get in the document given?

Do you mean MAC address? There is no PHY address. Since you are using a soft MAC, you get to program the MAC address. With a real product you have to request a block of MAC addresses (I believe from IEEE OUI). For your purposes, you just make one up.

Hi...:) I dont mean the MAC address.. I want to write a data to PHY.. Before the Core writes data to the Phy, the data register need to be set to the desired data and the control register must be configured with the Phy Address, Register Number and read or write option. This is how my Mii Control register looks. How should I give for the PHY? (We use Custom MAC) mii-core control register (regbase + 16) (write) Bit 15 -> 0 Bit 14 -> 1 Bit 13 & 12 -> 10 for Read and 01 for Write Bits[11..7] -> PHY addr [4..0] Bits[6..2] -> register no[4..0] Bit 1 -> 0 for write, 1 for read Bit 0 -> 0

I guess that you must be able to find it on the schematic of the board. Most PHYs have pins that must either be connected to ground or vcc to code the address. The other way is to add some code in your driver to guess the PHY address. The TSE Mac driver for Interniche does that. basically it tries every address until it gets an answer.

Help required on Ethernet with FPGA | Altera Community

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Altera_Forum
Honored Contributor
16 years ago
ok. In RMII you still need to provide a 50MHz clock, if it's not already provided by the board.

For the other components I don't have a Neek board, but I guess you'll also have to provide some clocks, and they should be mentioned in the documentation.
Altera_Forum
Honored Contributor
16 years ago
Hi Daixiwen and Jacobjones,

I integrated a custom MAC into my design. I transmitted a packet which I could see in the SignalTapII analyzer. But when I connected my NEEK board to another PC using crossover ethernet cable and when I ran Wireshark in that PC, I couldn't see any of the transmitted packets. Where could have been the problem...?

And one of the LEDs(orange indicating Link/Activity) is off for the moment when I send the packet and after that it is ON again. Please help me where the problem would be...
Altera_Forum
Honored Contributor
16 years ago
Hi Jacob Jones,

I wanted a help from you to solve this issue of mine. I use a Nios II/s cpu, on-chip memory, SSRAM, JTAG along with a custom MAC designed by H/W team. The problem that i face is this. I tried sending and receiving a single ethernet packet in the network, On receiving the ethernet packet i see some of the bytes in the frame missing for the reason that the DMA in my MAC faces arbitration issue with the cpu's data and instruction master and hence does not write ceratin packets in SSRAM. In my SOPC builder i had set the arbitration of cpu and data to be 1 and my MAC's DMA with 2.,but inspite of this i still see the frames missing.

So how do i solve this issue? Should i implement a FIFO to store packets and send only when my DMA receives the bus or should i use Nios II/f cpu that has a separate cache for data so that my processor does not interfere much with my MAC?

Should i add a DDR SDRAM in my design connecting it to the MAC's DMA and thereby having the "RESET and EXCEPTION" vector in SOPC to be SSRAM and also having the program,.rodata,.rwdata, stack and heap in NIOS to SSRAM so that my cpu's data and instruction master will acces only the SSRAM and my MAC accesing DDR SDRAM.

I had also downloaded your opencore MAC design and had a look at it. Did you face any of such issues? Can you also tell me what was the memory you had for program,.rodata,.rwdata, stack and heap in NIOS.

Expecting your response to solve my issue.

Regards

Renu.
Altera_Forum
Honored Contributor
16 years ago
First, a very common mistakes in designs with DMAs is to forget about the data cache. The DMA controller actually writes the correct data to memory, but the CPU doesn't see it because it's hidden by the data cache. It then reads the cached data instead of the one written by the DMA.
So the first thing you should do is to check that you use the alt_remap_uncached() function in the software when you read/write the data.

If it isn't a cache problem, and you indeed loose data because of arbitration problems, then I think it is a serious design problem in the DMA controller. It should contain a FIFO to buffer the data, and only try to access the memory when it is allowed to.
Using separate memories can be interesting to improve the performance, but the DMA core should be fixed first, before trying any optimizations.

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Help required on Ethernet with FPGA

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