Help required on Ethernet with FPGA

First, a very common mistakes in designs with DMAs is to forget about the data cache. The DMA controller actually writes the correct data to memory, but the CPU doesn't see it because it's hidden by the data cache. It then reads the cached data instead of the one written by the DMA.

So the first thing you should do is to check that you use the alt_remap_uncached() function in the software when you read/write the data.

If it isn't a cache problem, and you indeed loose data because of arbitration problems, then I think it is a serious design problem in the DMA controller. It should contain a FIFO to buffer the data, and only try to access the memory when it is allowed to.

Using separate memories can be interesting to improve the performance, but the DMA core should be fixed first, before trying any optimizations.