Hello, May I ask was your problem solved? How did you solved it. Thank you very much.

Hie Ying,

Your description of the problem statement is confusing. You need to describe the problem clearly for the community or Intel forum Application Engineers to understand your issue and provide suggestion. Your points described in #1 is known. After reading your point #2 is only when I can understand your issue.

Your problem statement is FPGA re-assert dev_sync_n during run time after CGS. Hence, this seems like you need to check the Converter settings configured in the FPGA and ADC. Also check the clocking and SPI register settings related to conveter are correct. Also if you are using subclass 1, then ensure the sysref generator is configured to generate sysref pulse, sysref pin assignment and polarity on board is correct and there is missing sysref pin between FPGA and IP core's port.

Regards,

Nathan