Hello, May I ask was your problem solved? How did you solved it. Thank you very much.

Hi Al,

First of all, very much appreciated your response.

I have Arrira 10 SoC FPGA and ADC12DJ3200 with 8 lanes of JESD204 Rx. ADC sampling clock is 3GHz and FPGA device clock is 300MHz with SYSREF at 3GHz/640.

I'm having the problem that dev_sync_n stays LOW even if FPGA has received x"BCBC" and rx_is_lockedtodata are HIGH from ADC chip. So ADC won't send data.

What would be your suggestions on this. Thank you very much.