Hello, Could anyone please explain and provide some resources, about how trustworthy is the code, automatically generated from a .bdf file in Quartus.

Hi,

"is there a possibility of unexpected error when complex schematics are converted to VHDL? How reliable is the VHDL code generated automatically from schematic? I am deciding if I should allow the tool to auto generate the VHDL or understand the schematic and manually design(expensive in terms of time). " ------- There is no issue recorded as such. If you allow to the tool to generate HDL, then tool will generates as per the algorithm inbuilt within it. The level of abstraction of the code generated by tool will be mostly behavioral, less visible & accessible to outside world as compared to manual design style.

Thanks,

Vicky