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MSchw39's avatar
MSchw39
Icon for New Contributor rankNew Contributor
6 years ago

Hello, community, what is the correct pinning of the 10CX085YU484 FPGA. The 10CX085.OLB schematic symbol from Intel shows a difference at pin H2, J1 , K2 and K3 in comparison to the Device Pin-Out-File 10cx085.xls. Is the .OLB file just obsolete?

H2 (VREFB3BN0), J1 (VCCIO3B), K2 (VCCIO3B) and K3 (VCCIO3B) in 10CX085.OLB H2, J1, K2, K3 are GND in the 10CX085.xls file.
AR_A_Intel's avatar
AR_A_Intel
Icon for Super Contributor rankSuper Contributor
6 years ago

We send you an email on update for pinning of the 10CX085YU484 FPGA