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I did not try it fully, since, I found it to be a bit complicated.
But, I found that this error in my case was due to trying to run the ref design under Win 7.
I believe it is possible to try it only under Win Xp 32 bit.
Give that a try maybe using VMWare.
I have moved on to another ref design which is much simpler, form Xillybus.
Try to google Xillybus and you should be there.
It gives a basic fee of the PCIe communications.
Stream read/ write. Writing/ reading to/from FPGA SDRAM etc.
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My dev. kit is stratix IV version and the download file doesn't exits (i have email them about this point)... Have u make it? what's ur dev. kit?
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