Altera_ForumHonored Contributor12 years agoGolden Top Level Pin Mapping Error Hello, I'm trying to compile the Golden_Top project provided in the examples of the SoC Development Kit. When compiling the fitter is generating the following errors: Error (175019): I...Show More
Recent DiscussionsAGILEX 5 cvp modeArrow AXE5 Eagle Board JTAG issuePDN file and PCB decouplingPCIe Example Design for Arrow EAGLE BoardCXL 2.0 support on the NEW Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile)Solved