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SKacc's avatar
SKacc
Icon for New Contributor rankNew Contributor
6 years ago

General I/O clarifications

Hi Please clarify the following queries 1. Does DIFFIO_TX_[B,T][#:#]p or DIFFIO_TX_[B,T][#:#]p acts as input? 2. Does DIFFIO_RX_[B,T][#:#]p or DIFFIO_RX_[B,T][#:#]n acts as output? 3. Does DIFFIO...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

In this case Clk13p is used as a ordinary output pin.Which will result in Quartus using up ordinary routing resources, whose delay will change each time you run your design through Quartus.

When we use dedicated pin for output, we achieve fast routing, so that the delay to these pins is minimized.

Regards

Anand

SKacc's avatar
SKacc
Icon for New Contributor rankNew Contributor
6 years ago

Hi Anand

I didn't understand. Can you please rephrase?

Also, Since CLK-P/N are dedicated clock input pins, does it impact if I use it as normal differential IO?

Regards

Srikanth Kacchu