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SKacc's avatar
SKacc
Icon for New Contributor rankNew Contributor
6 years ago

General I/O clarifications

Hi Please clarify the following queries 1. Does DIFFIO_TX_[B,T][#:#]p or DIFFIO_TX_[B,T][#:#]p acts as input? 2. Does DIFFIO_RX_[B,T][#:#]p or DIFFIO_RX_[B,T][#:#]n acts as output? 3. Does DIFFIO...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Srikanth,

You have to refer to the pin connection guidelines of respective device.

  1. DIFFIO_TX_<> when used for differential channel it is output pin, If not used for differential signaling, these pins are available as user I/O pins(input or output).
  2. DIFFIO_RX_<> when used for differential channel it is input pin, If not used for differential signaling, these pins are available as user I/O pins(input or output).
  3. If not used for differential signaling, these pins are available as user I/O pins(input or output).
  4. FPLL_<> can be used for clock output.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand

SKacc's avatar
SKacc
Icon for New Contributor rankNew Contributor
6 years ago

Hi Anand

For the 4th question, we have assigned CLK13p as single-ended LVTTL output in Intel Quartus software and didn't find any error.

What could be the reason?

Regards

Srikanth Kacchu