Hi,
a few thoughts on this:
- the "always" block is not sensitive to the reset; should be no reset in the real design, though, just something which would behave strange in the simulation
- does that PLL actually support a 256 kHz output clock? Sounds mighty low for a FPGA PLL. Was there any warning in the MegaWizard/IP Catalog?
- the reset signal seems to be active-low (I assume so because the name is "rst_n"), but your reset condition is "if (rst=1)"; typo?
- I assume "pwm_up" and "pwm_down" are push-buttons; are they debounced?
- are the "pwm_up" and "pwm_down" input signals maybe floating? If you accidentally mapped them to floating pins, they would wildly change the PWM duty cycle, which might cause the described behavior; actually, same for all input signals
I agree most of these points are unlikely to cause the described behavior, but maybe it's a combination of several effects...
I didn't see your simulation, so I have to assume it's correct. Also, I assume there are no timing issues. You didn't mention a static timing analysis, but 50 MHz sounds doable for just about any design in a MAX10.
One more thing: please consider using code-tags when posting code; your code lost all indentation and is hard to read when being posted as plain-text. Code tags can easily be inserted using that toolbar button with the "#" symbol.
Best regards,
GooGooCluster
Honored Contributor
