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Altera_Forum's avatar
Altera_Forum
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15 years ago

force Marvell 8E1111 PHY to 100MB on Cyclone III dev. Board

Hi, I'm implementing a MAC for a Cyclone III 3c120 Board in VHDL. It's PHY has an RGMII inferface but can be used for 10/100 MB speeds aswell. My state machine tells me that it's written to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for that answer! It works when I force my PC network card to 100MBit/s.

I've read the Marvell data sheet and I've sent a reset pulse and what you need to set the PHY control register. However, I still can't read from the PHY. Don't exactly know where to look for the Iniche Code, but I've left the PHY in autoneg. and setting my PC to 100MB does the job.

I've written a windows socket application (winsock) to receive the UDP packets which I'm sending from the FPGA. However, there seems to be a problem (maybe with my firewall). Because it only detects the packets when I start a wireshark capture! I know this might not be the right forum for that question, but maybe someone can help me on that??