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Honored Contributor
Honored Contributorforce Marvell 8E1111 PHY to 100MB on Cyclone III dev. Board
Hi, I'm implementing a MAC for a Cyclone III 3c120 Board in VHDL. It's PHY has an RGMII inferface but can be used for 10/100 MB speeds aswell. My state machine tells me that it's written to the...
Altera_ForumHonored Contributor
Honored ContributorYou can have a look at the schematic, or do as the Interniche driver does, i.e. try all the PHY addresses until you get an answer.
You shouldn't have to force the PHY chip into any mode, if your PC is limited to 100Mbits/s the PHY chip should detect it during autonegotiation and switch automatically to 100Mbits/s mode. IIRC the Marvel chip needs to be properly taken out of reset or it will behave strangely. Check that you provide a nice reset pulse to the chip during initialization, and have a look at the Interniche driver to see how it should be initialized through the MDIO registers after reset.
