Forum Discussion

Occasional Contributor

7 years ago

For the Max10 fpga peripheral clock it says: "Table 31. Peripheral Clock Interface Signals ... Note: To avoid functional failure, the required minimum peripheral clock frequency is 25 MHz"

I have a design that feeds both clocks of the ADC with a 2Mhz clock (from the PLL) and it seems to work fine for the Temperature Sense Diode. Our System clock for the FPGA is only 4Mhz. Does that mea...

GuaBin_N_Intel

Contributor

7 years ago

User must follow the note to run at minimum peripheral clock 25MHz for ADC core clock. Once violated, it will cause unexpected result when running it on hardware/board.

Forum Discussion

For the Max10 fpga peripheral clock it says: "Table 31. Peripheral Clock Interface Signals ... Note: To avoid functional failure, the required minimum peripheral clock frequency is 25 MHz"

Recent Discussions

Cyclone 10 LP Evaluation Kit - Documentation

AGILEX 5 cvp mode

Arrow AXE5 Eagle Board JTAG issue

PDN file and PCB decoupling

PCIe Example Design for Arrow EAGLE Board