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Mentz's avatar
Mentz
Icon for New Contributor rankNew Contributor
5 years ago
Solved

First vhdl design, building a bit memory

Hi all, I starting with vhdl, and build this first design, Than I wrote to a cyclone II device and got this: From this circuit, I was expecting that dff output goes high at DFF cl...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi,

    I tried to simulate the design; there is a spike in the DFF_Clock that causes the output of signal DFF_output as shown in waveform.PNG.

    You may consider to remove the JK FF and AND gate.

    Thanks.

    Best regards,

    KhaiY

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I tried to simulate the design; there is a spike in the DFF_Clock that causes the output of signal DFF_output as shown in waveform.PNG.

You may consider to remove the JK FF and AND gate.

Thanks.

Best regards,

KhaiY

Mentz's avatar
Mentz
Icon for New Contributor rankNew Contributor
5 years ago

Hi KhaiY,

I've changed my design, excluding AND gate and and some other changes and it worked,

thanks for your time and efforts

Mentz