New Contributor
New ContributorNo actually, I intend to synthesis this code to put into a device. I couldn't simulate it because the input actually comes from vJTAG server communication meaning from a separate python code, so I'm not sure how to simulate that in Quartus alone. The results I'm referring to is what I observe after synthesizing it into the device.
If the time delay can't be simulated by "#10" alone how can I write the Verilog code to pause/delay for 10 clock cycles? Furthermore if I use a display command ($display) where would I see the results I'm trying to display?
The non-blocking statements I avoided because I was of the understanding that non blocking statements are executed without an order, whereas blocking statements ensure that the previous statement has been executed before moving to the next. Kindly elaborate as to why non blocking statements would not be an issue here.
Also please help highlight any other part of the code which is not going to do some of the things my comments indicates I want it to do.
Thank you for your help and response!
Ani
