Forum Discussion
New ContributorFFT Intel FPGA IP
Regular ContributorHi,
Thanks for your update. Please feel free to correct me if any of the following understandings are inaccurate:
- Using the FFT Intel FPGA IP (version 19.1) in Bi-directional mode, asserting the invert input signal appears to result in an output sequence that does not match the expected Python-generated values.
- In Reverse mode with the same IP version, the output also seems to be incorrect.
- However, when using the Variable Size FFT Intel FPGA IP in Inverse VFFT mode, the output aligns correctly with the Python values.
From what I understand, the FFT Intel FPGA IP (version 19.1) was previously primarily intended for legacy devices. Would it be feasible for you to use the Variable Size FFT Intel FPGA IP as a workaround?
Please let me know if you have any concerns or need further clarification. Thank you.
Best regards,
Chee Pin
binfu1Hi,
Thanks for your reply. I need to change FFT mode (forward and inverse FFT) in the runtime, so the FFT Intel FPGA IP is my best choice. Although I can modify the Variable Size FFT Intel FPGA IP to realize the same function, I want to make sure the problem mentioned above caused by the IP itself, instead of improper use of mine.
Best regards.
- CheepinC_altera
Hi,
Thanks for your clarification. I’ll continue investigating the behavior of the FFT IP v19.1 and will keep you updated on any findings.
In the meantime, I understand that the Variable Size FFT Intel FPGA IP allows for a static configuration of Forward/Inverse mode during IP setup. Could you kindly elaborate on how you modified the IP to enable runtime switching between FFT modes?
Appreciate your insights. Thank you.
Best regards,
Chee Pin- binfu1
Hi，
The compute flow of inverse FFT contain forward FFT, so we can realize inverse FFT based on Variable Size FFT Intel FPGA IP (forward mode) by adding missing calculation steps.
Best regards.
