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Altera_Forum
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7 years ago

Failed programming at 85%

Hello All, I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

I think I figured out the problem. It seems that the Unique Chip ID core uses JTAG signals internally to read the ID. And in my code, the core's reset signal is initialized as de-asserted. Consequently, when the chip loading process reached 85% and the circuit (including the Unique Chip ID core) was activated, the Unique ID core immediately tried to use JTAG to read the ID. This interfered with the finalization of the loading process (which was also via JTAG) and caused the error.

The solution was simply to initialize the core's reset signal to be asserted and wait a little bit for the loading process to finish before de-asserting it.

Arintel