Ethernet with NiosII on Cyclone III FPGA Board?

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I would like to use the ethernet on the cyclone 3c120 fpga development board with NiosII and the Niche TCP/IP stack. Anybody has done this already or knows about a quick solution? The CD of this development kit containts only a basic nios2 reference design..

Thanks for help,

Christian

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Unfortunately, Altera doesn't have a reference ethernet design for this board, at least yet, but a few of us do have it working.

For the FPGA design, PHY pinouts must be defined from the schematic, the RGMII interface hooked up to the MAC, a PLL implemented to create the gtx_clk, and a bit of work done in the auto-generated TimeQuest TSE constraint file. (See this thread http://www.alteraforum.com/forum/showthread.php?t=3040)

The only soft MAC supported by the NicheStack is the Altera Triple Speed Ethernet. For the Nios software, simply enable uC/OS and the NicheStack, and select the tse_mac. The tse_mac driver assumes a very specific fpga design, using scatter-gather DMA to interface to the MAC, see chapter 6 of the Triple Speed Ethernet MegaCore user guide.