Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI can see two problems:
Register access: you release the write signal too soon. Try to keep it to 1 and see if waitrequest is released after a while. You should only release write when waitrequest is at 0. Packet send: the sop is never seen by the TSE because you release it before the rising edge of the clock. More generally the data is changing faster than the clock so I think that you are not generating the packet with the same clock than ff_tx_clk.