Ethernet with DSP Dev. Kit Cyclone III (no NIOS)

I have the same OpenCore plus window, but it is very important that you don't close the alert window with that message and the "cancel" button. If you do that, it will disable the TSE until you configure the FPGA.

If you are reading or writing, then you aren't in an idle cycle.

Could you show a Signaltap acquisition of the signals on the avalon interfaces when you attempt to write to the TSE, and when you send a packet?

Does your design meet timing requirements? No critical warnings from Timequest?