Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- waitrequest shouldn't be high when you are writitg or reading. If it still is, then you have a problem. --- Quote End --- I think the reason why I do not see the packets in wireshark is the problem with the waitrequest signal. When I program the device, the OpenCore Plus Status message displays: Time remaining: unlimited This takes me aback, I thought I could use it only for one hour without license. What did it display in your design? I have put ff_rx_rdy, read, write, set and reset to GND. Then I opened Timequest (which I use for timing analysis) and generated a SDC file from QSF for my project. In my project I included myproject_top.sdc and tse_constraints.sdc. For Tcl Script File I use tse_constraints.tcl, which I did not modify. The clock signals are defintely not stuck and reset is only asserted once on startup. On the pin assignment I have altera_reserved_tck, altera_reserved_tdi, altera_reserved_tdo and altera_reserved_tms which I can't assign to the pins according to the datasheet. Normally I can see every packet in wireshark, no matter how badly formatted it is. Once I used a windows-program to send a packet consisting of some random bytes and wireshark captured it. So I think wireshark is not the problem. In the avalon specification it says: An Avalon-MM slave may assert waitrequest during idle cycles. Maybe the TSE is in a idle cycle for any reason.