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This means that when you address the component yourself, you need to divide the address by four. i.e. supply "00000010" on the address bus to access the config register.
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OK, thank you. I didn't know this.
So until now the following things work:
- Physical ethernet connection (LEDs are on)
- Programming of the TSE Register (command_config)
- Time constraints (I included the default tse_constraints.sdc, but I did nothing with timequest)
- tx_clk,rx_clk: 125 MHz without phase shift
Now I am trying to send packets but I cannot see them in wireshark (
http://www.wireshark.org/). Maybe the problem is that I do not know which is the right preamble to use in the ethernet frame. I couldn't find it in the TSE Guide. With SignalTap I have seen that rgmii_out and tr_control (enet_tx_en) is always low (0). I already checked that it is
not because of the OpenCore Plus Hardware Evaluation of the TSE.
When I try to send packets, the TX LED is flashing, but I can't see the packets in wireshark. My packet is more than 42 Byte long, so it is not too short. I still wonder why waitrequest is always high (1). Maybe it is low active...
Should the write enable Signal be asserted when the packet starts or when the preamble starts?
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