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Mahsheed's avatar
Mahsheed
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2 years ago
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Ethernet access via FPGA in DE10 nano board

Hello, I am using DE10 nano board for my project, and I want to use its ethernet with FPGA. I planned to use TSE Ethernet IP core and link it with FPGA pins that are routed with PHY IC. Now when I ...
Fpga Devkit
Mahsheed's avatar
Mahsheed
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2 years ago

Add the HPS IP and designate these pins as "loaner I/O"
Can you please tell me how to do that?

  • Mahsheed's avatar
    Mahsheed
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    2 years ago

    Thank you very much for sharing the knowledge with me. It really saved me

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    Mahsheed
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    2 years ago

    Hello, Can you please answer my few queries as I am new to qsys and intermixing of FPGA and HPS.

    1) I generated HDL file (SOC_system.v) from qsys after loaning my Pins. Do I just need to add that .v file into my quartus prime bdf file and make necessary connections and add this bdf file into my FPGA? (just like I used to do with my pure FPGA code)

    2) I used a demonstration project to use QSYS, and it gives a lot of IO when I generate HDL file (SOC_system.v). Its difficult for me to handle all those IOs in my bdf file, as I only need Loan IO pins from HPS. So my concern is if I can remove those connections in HPS_0 before generating HDL file? If so, which signals can be removed safely without effecting the HPS loan functionality?

    Thanks in advance