Error:14566 - Fitter cannot place 2 periphery components due to conflicts with existing constraints (2 IO PLLs).

I got this error while instantiating an external IO PLL to two Serdes channels in LVDS for arria 10 device.

I need to provide two high speed clocks into one bank (eg Bank 3B) where i use two LVDS serdes channels which receive one high speed clock each into theirs IO PLL(internal one). But Quartus- Fitter shows the above mentioned error.

so cant we use an IO PLL (internal/external) to every serdes channels available in a bank??

Please let me know Is there any alternate ways to provide two clock sources to two LVDS serdes channels.

Thanks in advance.