Error with Intel altera_emif IP while creating dts file

Hi Matt ,

It's me Aida. Welcome to Intel Community.

Please accept my apology for the delay in response.

I believed this is duplicate case from this link here --> https://forums.intel.com/s/question/0D50P00004doLufSAE/a10-soc-issue-with-sopcinfo-file-while-generating-dts-file

I have go through the details in above case (in provided link). To be honest, this is not my expertise area but I will try my best to help you. 😊

I did some internal searching, I suspect the issue is due to the system not recognize any driver for emif. But seem like you only need to access the FPGA EMIF from HPS as a flat memory, maybe you can try to modify the DTS to flat memory as below. Shown below is just the example code to modify. Please try this on your own design code and see if you still can access the address from HPS.

Example:

// emif_0_ecc_core: unknown@0x100000040 {

// compatible = "unknown,unknown-16.1";

// reg = <0x00000001 0x00000040 0x40000000>;

// clocks = <&emif_0_arch 0>;

// }; //end unknown@0x100000040 (emif_0_ecc_core)

memory {

device_type = "memory";

reg = <0xc0000000 0x20000000>;

};

Hope this helps.

Thanks

Regards,

Aida