Error running Very Basic Operation on Stratix 10 SX SoC Dev Kit

Hi,

May I know which Quartus and SoC EDS version you are using?

And could you provide the full part number your Stratix 10 Device? Is it the L-tile or the H-tile version?

Regards

Dear RDoev1,

Which Quartus version are you using for the design?

Is the issue happening with cold or warm reset?

We had a similar issue in the past where the failure was due to SDRAM ECC + Cold reset. The delta between SOCEDS 18.0 and 18.1 is SDRAM ECC is enabled at 18.1 and this caused the issue with SDRAM calibration failures.

Could you please run a test and disable ECC disabled on the HPS-EMIF?

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/emif/2018/why-does-the-hps-hang-or-emif-calibration-fails-during-cold-rese.html

Hope this helps.

Thanks

Regards,

Aida