Forum Discussion
Kay
New Contributor
7 years agoHi,
1. Does design use PR?
2. If so, how are partial bitstream transported to the FPGA in user mode.
I could not find answers from the design.
Thanks
ywang161
New Contributor
7 years agoHI,
1.Yes the design uses PR. You can find this line in the tcl script:
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to counter_0
2.Due to the problem in fitter, I'm not able to generate a partial bitstream. However it is supposed to be transported to FPGA through the PR Controller IP with Avalon MM interface.